\doxysection{FMAC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_f_m_a_c___type_def}{}\label{struct_f_m_a_c___type_def}\index{FMAC\_TypeDef@{FMAC\_TypeDef}}


Filter and Mathematical ACcelerator.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_a_c___type_def_ab627e4d4444b56ff92ea717c4f4935ef}{X1\+BUFCFG}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_a_c___type_def_a25a1aceaea1cd286f8d70861e9449b84}{X2\+BUFCFG}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_a_c___type_def_a5cfb4951153e279dc138fc485e8e894b}{YBUFCFG}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_a_c___type_def_a0fc51e98084ab6e4d25776f3687b532d}{PARAM}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_a_c___type_def_afe75a3c4c2d474f995660f69e8885075}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_a_c___type_def_a4db0532c8e24b84f1c7501a5374a40d6}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_a_c___type_def_adf3bcc3b2485455631fc486806eaa2f8}{WDATA}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_m_a_c___type_def_a8fe14a79ed2d4e19969ecee98df7ef24}{RDATA}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Filter and Mathematical ACcelerator. 

\label{doc-variable-members}
\Hypertarget{struct_f_m_a_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_f_m_a_c___type_def_afe75a3c4c2d474f995660f69e8885075}\index{FMAC\_TypeDef@{FMAC\_TypeDef}!CR@{CR}}
\index{CR@{CR}!FMAC\_TypeDef@{FMAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_f_m_a_c___type_def_afe75a3c4c2d474f995660f69e8885075} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMAC\+\_\+\+Type\+Def\+::\+CR}

FMAC Control register, Address offset\+: 0x10 \Hypertarget{struct_f_m_a_c___type_def_a0fc51e98084ab6e4d25776f3687b532d}\index{FMAC\_TypeDef@{FMAC\_TypeDef}!PARAM@{PARAM}}
\index{PARAM@{PARAM}!FMAC\_TypeDef@{FMAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PARAM}{PARAM}}
{\footnotesize\ttfamily \label{struct_f_m_a_c___type_def_a0fc51e98084ab6e4d25776f3687b532d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMAC\+\_\+\+Type\+Def\+::\+PARAM}

FMAC Parameter register, Address offset\+: 0x0C \Hypertarget{struct_f_m_a_c___type_def_a8fe14a79ed2d4e19969ecee98df7ef24}\index{FMAC\_TypeDef@{FMAC\_TypeDef}!RDATA@{RDATA}}
\index{RDATA@{RDATA}!FMAC\_TypeDef@{FMAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RDATA}{RDATA}}
{\footnotesize\ttfamily \label{struct_f_m_a_c___type_def_a8fe14a79ed2d4e19969ecee98df7ef24} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMAC\+\_\+\+Type\+Def\+::\+RDATA}

FMAC Read Data register, Address offset\+: 0x1C \Hypertarget{struct_f_m_a_c___type_def_a4db0532c8e24b84f1c7501a5374a40d6}\index{FMAC\_TypeDef@{FMAC\_TypeDef}!SR@{SR}}
\index{SR@{SR}!FMAC\_TypeDef@{FMAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_f_m_a_c___type_def_a4db0532c8e24b84f1c7501a5374a40d6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMAC\+\_\+\+Type\+Def\+::\+SR}

FMAC Status register, Address offset\+: 0x14 \Hypertarget{struct_f_m_a_c___type_def_adf3bcc3b2485455631fc486806eaa2f8}\index{FMAC\_TypeDef@{FMAC\_TypeDef}!WDATA@{WDATA}}
\index{WDATA@{WDATA}!FMAC\_TypeDef@{FMAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WDATA}{WDATA}}
{\footnotesize\ttfamily \label{struct_f_m_a_c___type_def_adf3bcc3b2485455631fc486806eaa2f8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMAC\+\_\+\+Type\+Def\+::\+WDATA}

FMAC Write Data register, Address offset\+: 0x18 \Hypertarget{struct_f_m_a_c___type_def_ab627e4d4444b56ff92ea717c4f4935ef}\index{FMAC\_TypeDef@{FMAC\_TypeDef}!X1BUFCFG@{X1BUFCFG}}
\index{X1BUFCFG@{X1BUFCFG}!FMAC\_TypeDef@{FMAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{X1BUFCFG}{X1BUFCFG}}
{\footnotesize\ttfamily \label{struct_f_m_a_c___type_def_ab627e4d4444b56ff92ea717c4f4935ef} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMAC\+\_\+\+Type\+Def\+::\+X1\+BUFCFG}

FMAC X1 Buffer Configuration register, Address offset\+: 0x00 \Hypertarget{struct_f_m_a_c___type_def_a25a1aceaea1cd286f8d70861e9449b84}\index{FMAC\_TypeDef@{FMAC\_TypeDef}!X2BUFCFG@{X2BUFCFG}}
\index{X2BUFCFG@{X2BUFCFG}!FMAC\_TypeDef@{FMAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{X2BUFCFG}{X2BUFCFG}}
{\footnotesize\ttfamily \label{struct_f_m_a_c___type_def_a25a1aceaea1cd286f8d70861e9449b84} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMAC\+\_\+\+Type\+Def\+::\+X2\+BUFCFG}

FMAC X2 Buffer Configuration register, Address offset\+: 0x04 \Hypertarget{struct_f_m_a_c___type_def_a5cfb4951153e279dc138fc485e8e894b}\index{FMAC\_TypeDef@{FMAC\_TypeDef}!YBUFCFG@{YBUFCFG}}
\index{YBUFCFG@{YBUFCFG}!FMAC\_TypeDef@{FMAC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{YBUFCFG}{YBUFCFG}}
{\footnotesize\ttfamily \label{struct_f_m_a_c___type_def_a5cfb4951153e279dc138fc485e8e894b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FMAC\+\_\+\+Type\+Def\+::\+YBUFCFG}

FMAC Y Buffer Configuration register, Address offset\+: 0x08 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
